Study note of LabVIEW FPGA (3) — Multi-line transmission

I came up with this problem when I was doing my project. There are more than 66 parallel pinouts on the Spatial Light Modulator (SLM) chip to be controlled. I generated the commands on the computer and then send them to the fpga via DMA FIFO. It worked fine when there were only 64 lines. I can transfer a 1D U64 array to the target and then split each U64 data to 64 booleans.
See also the example ‘DMA buffered acquisition’ in LabVIEW 2009.

When there are 66 bits, I just created 2 FIFOs for the first place, one of which was type U64 while another is U8. I found it very hard to synchronize the 2 FIFOs. Some memory (I can’t remember exactly where it came from) recalled me using case structure to decimate the 1D array. So I interleaved the data to a 1D U32 (because there are 32 bits on Bus A and Bus B) array, and decimated them on the fpga side. By doing this I *wasted* 32×3-66=30 bits per command, which is tolerable and flexible.
Host vi:

Target vi:

We set up the order of procceding by creating a type defined enum (Enum ‘Bus B’ in the figure) and telling the state machine which state the next should be. Note that we need to create a for loop in each iteration. Because we want to dequeue the buffer several times to achieve the commands for all lines.

Related Posts: Study note of LabVIEW FPGA (1)                           Study note of LabVIEW FPGA (2)

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